ASIC Physical Design Engineer Lead - 80758 Job Listing at AMD in Austin, TX (Job ID 679795200)

Description

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Title : Lead Physical Design Engineer

The Role :

In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The Implementation team leads the Synthesis/Timing closure/Clock domain crossing and Design for test aspects for our leading edge I/O subsystem IP which include both industry protocols like PCIe/SATA as well as link-layer IPs which are a integral part of AMD's infinity fabric network. The team takes care of very complex, sophisticated and high speed (>2G) design which is constantly pushing the boundaries with multiple implementation challenges. The expectation is to take the team and build a future roadmap for introducing shift left strategies like Physcial Implementation at IP level, introduce new tools and flows for Clock Domain Crossing, improve Design for Test Capability and come up with strategies to cater to high speed design timing closure.

• Strong analytical thinking and problem solving skills, excellent attention to detail
• Must have good collaboration and interpersonal skills
• Excellent communication skills with leadership qualities

The Distributed crossbar I/O & Chiplet interconnect technology team take care of multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer. This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis, Clock Domain Crossing, Gate Power measurement, Static timing Analysis, LINT & Design for Testing. The team also persistently works on reducing the power envelope of the design to cater to the growing demand for low power IPs while maintaining the overall bandwidth and latency budgets.

Experience with different implementation domains outlined above. The candidate may have led a team of engineers in his or her current role. Giving the nature of IP, Physical design experience is beneficial.

*LI-AP1

Requisition Number: 80758 
Country: United States State: Texas City: Austin 
Job Function: [[jobSubFunction]]  

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