Lead DFT Engineer Job Listing at AMD in Hyderabad, TS (Job ID 79478-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

MTS SILICON DESIGN ENGINEER  

THE ROLE

The Test Development team is driving quality and manufacturability for some of the industry's most advanced MPSoC designs at 7nm and beyond. As a Member Technical Staff(MTS) Silicon Design Engineer, you will play a pivotal role in shaping how complex, high-performance silicon is tested, validated and delivered to customers across automotive, data center, machine learning and high-speed connectivity markets.

This role offers deep, hands-on exposure to Scan, MBIST and iJTAG test development on large, heterogeneous SoCs that integrate ARM-based processors alongside critical, high-value IPs. You will work at the intersection of design, test and manufacturing — partnering closely with RTL designers to ensure robust DFT insertion, collaborating with test engineers to translate DFT intent into scalable ATE programs and engaging with product and yield teams to enable stable, high-volume production. The environment is fast-paced, highly collaborative and impact-driven, offering strong technical ownership, continuous learning and visibility across the full silicon lifecycle.

THE PERSON

You are a strong communicator and team player who thrives in a globally distributed, collaborative environment. You embrace technical challenges, adapt quickly to changing priorities and take ownership of complex problems through to resolution. A proactive mindset, curiosity to learn and commitment to quality are key to success in this role.

KEY RESPONSIBILITIES

• Partner closely with RTL design teams to define, review and ensure correct insertion of DFT architectures across SoC and IP designs.
• Develop, implement and verify robust DFT schemes for hard IPs and FPGA-based designs.
• Own test development for digital logic using scan compression and multiple fault models, including stuck-at, transition and path-delay.
• Develop and validate MBIST architectures and patterns to ensure high coverage and production readiness.
• Lead debugging of scan, MBIST and pattern-related issues on bench and ATE, driving root-cause analysis and resolution.
• Collaborate with NPI, Test Engineering and Product teams to deliver high-quality, production-ready test content on schedule.
• Support diagnosis and yield improvement efforts throughout the product lifecycle.
• Design and implement firmware-driven, cost-effective test strategies with built-in diagnostic capabilities.
• Optimize test methodologies to improve coverage, reduce test cost and enhance overall product quality.
• Contribute to continuous improvement by mentoring team members and sharing best practices.

PREFERRED EXPERIENCE

• Experience designing and implementing complex, chip-level DFT architectures for advanced SoCs.
• Hands-on experience with DFT implementation, including Scan and Scan Compression, at IP and SoC levels.
• Experience using DFT and ATPG tools across stuck-at, at-speed and path-delay fault models.
• Proficiency in RTL logic design using Verilog, with working knowledge of synthesis and static timing analysis.
• Experience developing testbenches and running simulations in RTL, gate-level and SDF environments.
• Working knowledge of MBIST architectures and pattern development is preferred.
• Familiarity with FPGA design and synthesis flows is a plus.
• Exposure to post-silicon debug, bench setup and ATE-based validation is a plus.
• Comfortable working in Linux environments and using scripting languages such as Perl, Tcl or Python.

ACADEMIC CREDENTIALS

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related field is preferred.
• Formal education or training with a focus on digital design, DFT or test methodologies is desired.
• Tessent Scan, ATPG or MBIST certifications are a plus.

LOCATION:

Hyderabad, India

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.