MTS Silicon Design Engineer ( Physical Design Flow & Methodology Engineer) Job Listing at AMD in Bengaluru, KA (Job ID 40031-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS – Physical Design Flow & Methodology Engineer

THE ROLE: 

As a member of the Strategic Silicon Solution Group, you will help bring to life cutting-edge designs. As a member of the PD flow & methodology team, you will work on new physical design flow methodology/automation/regression to release quality instructions to PD tile/block/partition team and will work closely with the PD Tile, PD Integration and CAD team across various geographies to achieve first pass silicon success.

THE PERSON:

A successful candidate will work on latest cutting edge PD flow, methodology and efficiency improvement on lower nodes like 5/3/2nm. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. You are a team player who has excellent communication skills and experience collaborating with multi-level functional teams across various geographies. The person should be self-motivated, practical and enjoys working with people.

KEY RESPONSIBLITIES:

• Automation to improve design PPA (Power, Performance, Area) and ensure a high quality design environment
• To increase the competitiveness of each stage in AMD design flow
• Support/mentor/coach/guide Physical Designers in use of AMD internal flows for timing closure, place and route optimizations, logic ECOs and physical verification signoff.
• Doing flow regression/validation with various levels of Full chip Floorplan Input data, library, CAD flow, technology and project based flow requirement and delivering a quality flow label/instruction to tile/block owners for tile level low power place-n-route and ECO implementation
• Updating project-based settings based on design, technology and guidelines requirement
• Creating instructions for functional ECO, leakage power recovery, design input change, etc.
• Working with CAD team for any outstanding issues and to improve flow efficiency.
• Ability to prioritize and solve various issues reported by tile/partition PD team.
• Maintain tile PD release data.

• Outstanding problem-solving and analytical skills
• Outstanding interaction skills while communicating both written and verbally.
• Ability to work with multi-level functional teams across various geographies.
• Highly organized, able to prioritize and balance multiple work streams while working to meet and exceed goals

PREFERRED EXPERIENCE:

• 8+ years of strong experience in Physical Design Implementation/Automation and optimization for quality.
• Experience in AMD block place-n-route and ECO implementation using TileBuilder is a plus.
• Experience with ICCII/Fusion Compiler/Primetime/Redhawk/Calibre
• Experience in low power physical design implementation flows ranging from RTL design through synthesis, place and route, timing closure and physical verification
• Experience in lower technology nodes like 5/3/2nm
• Scripting language experience: TCL, Perl, Python, Makefile, Shell preferred. 
• Knowledge in Perforce (or GITHUB or any file control version system).
• Familiarity with machine learning tools and techniques will be a plus

ACADEMIC CREDENTIALS:

• Bachelors or Master's degree in Computer/Electronics/Electrical Engineering 

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.