Principal, HSIO Validation Lead Job Listing at AMD in Santa Clara, CA (Job ID 75604-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE:

The High‑Speed IO (HSIO) validation lead owns the end‑to‑end validation strategy and execution for high‑speed interfaces across all CPU‑based platforms, spanning data center servers and AI platforms that integrate a host CPU. In this highly visible role, you will actively work with PHY design team, SIPI team and participate in validation and debug of high-speed IO circuits to enable the world's premiere products.

KEY RESPONSIBILITIES:

• Lead the validation strategy, planning, and execution for high-speed IO interfaces (e.g., PCIe Gen6/Gen7, UALink, XGMI) across multiple systems.
• Define and drive comprehensive validation test plans, including pre-silicon and post-silicon activities, compliance, margining, and debug methodologies.
• Collaborate closely with cross-functional teams (design, architecture, board, firmware, and test engineering) to ensure robust coverage and timely issue resolution.
• Oversee the development and deployment of automated test infrastructure, lab setups, and data analysis pipelines for high-speed interface characterization.
• Guide root cause analysis for SI/PI issues, system-level failures, and interoperability challenges, working with internal and external partners as needed.
• Track validation progress, report status and risks to program management, and ensure deliverables meet quality and schedule commitments.

PREFERRED EXPERIENCE:

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field; 8+ years of relevant experience in high-speed IO validation or silicon/system validation.
• Deep technical expertise in high-speed serial interface standards (e.g., PCIe Gen5/Gen6, CXL, Ethernet) and associated compliance/debug tools (e.g., oscilloscopes, BERTs, protocol analyzers).
• Knowledge of Tx/Rx equalization techniques and circuits, including CTLE, DFE, and de-emphasis, as well as CDR architectures and implementations.
• Proven track record of leading validation teams or projects, with strong organizational and communication skills.
• Hands-on experience with lab bring-up, test automation (Python, C/C++, or similar), and data analysis for SI/PI and functional validation.
• Solid understanding of signal integrity, power integrity, and system-level debug methodologies.
• Ability to work effectively in a fast-paced, cross-functional environment and drive issues to closure.
• Passion for quality, innovation, and continuous improvement.

ACADEMIC CREDENTIALS: 

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
• 8+ years of relevant experience in high-speed IO validation or silicon/system validation.

LOCATION:

Santa Clara, CA

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.