Senior Design Verification Engineer – SerDes IP Job Listing at AMD in Bengaluru, KA (Job ID 76590-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE

We are looking for a Senior Design Verification Engineer to join our SerDes IP team focused on high-speed wireline transceivers (e.g., PAM4 at 56G/112G and beyond). In this role, you will verify complex SerDes digital and mixed-signal-adjacent subsystems including adaptation/calibration loops, control state machines, datapath DSP blocks, and firmware-configurable features using SystemVerilog/UVM and robust reference modeling.

You will work closely with architecture, design, circuit/modeling, and validation teams to ensure correctness, coverage, and high confidence across PVT, jitter/noise stress conditions, and protocol/feature configurations.

THE PERSON

You enjoy verifying systems where behavior emerges from algorithms + state + timing (not just combinational logic shows up in waveforms). You can translate high-level requirements into a rigorous test plan, build testbench infrastructure that scales, and debug issues with a structured approach using waveforms, logs, assertions, coverage, and model correlation.

You communicate clearly, handle ambiguity by asking the right questions, and drive closure by aligning design intent, models, and verification.

KEY RESPONSIBILITIES

• Own verification of SerDes digital IP blocks such as:
  • DSP datapath blocks (FFE/DFE/filtering, slicing/decoding, saturation/rounding)
  • Control loops and adaptation logic (CDR/MM-like updates, EQ adaptation, calibration flows)
  • ADC interface logic and calibration support (gain/offset/deskew control, monitoring hooks)
  • Clocking/control interfaces and configuration registers
• Develop verification plans with clear coverage goals:
  • Feature/config coverage, corner-case stimulus, error injection, reset/power-state coverage
• Build and maintain UVM environments:
  • Agents, drivers, monitors, sequences, scoreboards, reference models
  • Transaction-level logging and debug infrastructure for fast root-cause
• Create realistic stimulus:
  • PRBS patterns, framed streams, randomized bursty traffic, backpressure
  • Jitter/noise/error injection at the digital interface level (as supported by models)
• Drive verification closure using:
  • Functional coverage, assertion-based checks, scoreboarding/model checking
  • Regression triage and failure minimization
• Support simulation acceleration and emulation where applicable:
  • Runtime optimization, stable builds, reproducible debug flows
• Collaborate cross-functionally with modeling, circuit, and firmware teams:
  • Align RTL behavior to architectural intent and system models (e.g., time-domain/AMI-like)
  • Provide actionable bug reports with clear expected vs observed behavior
• Mentor junior engineers and raise team-wide verification quality and reusability

REQUIRED EXPERIENCE

• 5+ Years of experience in the design verification.
• Strong hands-on experience with SystemVerilog and UVM 
• Proven ability to build scoreboards / predictors / reference models for algorithmic blocks
• Solid understanding of verification fundamentals:
  • reset/clocking, CDC safety concepts, corner-case stimulus, coverage closure, assertions
• Comfortable with debugging complex issues using waveforms + logs + model correlation
• Strong programming skills in C/C++ or Python (for modeling, stimulus generation, test infra) is a big plus.

PREFERED EXPERIENCE

• SerDes domain experience is not a must. But will be helpful. For example:
  • Exposure to SerDes / wireline concepts:
    • PAM4 vs NRZ, ISI, equalization (CTLE/FFE/DFE), adaptation loops, CDR concepts
  • Experience verifying DSP-style logic:
    • fixed-point arithmetic, saturation, rounding, pipeline latency, parallel/serialized datapaths
• Experience with performance/throughput verification and stress testing:
  • backpressure, multi-stream scenarios, long regressions, convergence behaviors
• Experience supporting post-silicon bring-up correlation or debug hooks

ACADEMIC CREDENTIALS

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.