Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
SMTS SILICON DESIGN ENGINEER
THE ROLE:
As a member of the Server SOC PD group, you will help bring to life cutting-edge designs.
As a Senior technical contributor responsible for SoC / full-chip Physical Verification signoff (DRC/LVS/ERC/DFM/Antenna/PERC) and PV methodology ownership, partnering cross-functionally to ensure tapeout-quality delivery on advanced nodes
Job Description
- Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC (Mostly Working on Calibre tool)
- Experience in IO, Bump planning and fullchip RDL generation for Power & IO/Signals
- Work on physical verification (DRC/LVS) of state-of-the-art SOCs/digital IPs/blocks at cutting edge technology nodes of various foundries.
- Work hands-on to solve critical design and execution issues related to physical verification and sign-off
- Strong Technical problem and debugging solving.
- Own physical verification and sign-off flows, methodologies and execution of SoCs
Preferred Experience:
- 12+ years' experience in ASIC Design with relevant Physical Design Skills
- Minimum BSEE/CE, or equivalent degree, Masters is preferred.
- Experience with physical verification checks DRC, LVS, Antenna, ERC, PERC, ESD etc for SoC/Full-chip-level and/or block-level
- Preferably worked on 3nm/5nm/7nm/14nm/20nm nodes at the major foundries
- Experience in PV support a larger team members.
- Work on Fullchip RDL power generation in top level, Bump planning, IO RDL routing
- Experience in debugging LVS issues at chip-level with complex analog-mixed signal IPs
- Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
- Experience in physical verification of padring, corner pads, seal ring, DCM, RDL routing, bumps and other full-chip components
- Experience with ERC rules, PERC rules, ESD rules has an added advantage.
- Ability to plan and work independently and coordinate with cross-functional teams.
- Experience in PnR tools like ICC2/Innovus with regards to physical convergence must.
- EDA Tools: Mentor (Calibre), Synopsys (ICV) & icc2/innovus
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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