Senior Vivado Tools & Methodology Engineer – Technical Marketing Job Listing at AMD in San Jose, CA (Job ID 89200-en-us)

Description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

You will own how FPGA and Adaptive SoC designers build with Vivado. This is a hands-on, deeply technical role on the AMD-AECG Technical Marketing team: you define the tool flows, features, and design methodologies our customers depend on, and you validate them against real designs before they reach the field. Your scope spans a broad set of Vivado areas — simulation and verification, RTL and IP-based design, collaborative and team-based design, implementation and timing closure, IP protection and security, and tool deployment.

Technical Marketing sits between R&D, product planning, applications engineering, the field, and top-tier customers. You are the person who understands the design flow end to end, who customers escalate to, and whose judgment shapes what gets built next. The environment is fast moving, global, and focused on emerging technologies. We operate with an agentic AI-first mindset and expect team members to actively incorporate AI into how they work.

This role is scoped to grow. A strong performer will progressively take on broader Vivado ownership, more direct influence over the roadmap, and a leadership position within the Technical Marketing organization.

You have lived in FPGA or ASIC design tools and can hold a credible technical conversation with a senior designer and an executive on the same day. You understand customer concerns and pain points at a deep technical level and are driven to find the best solution rather than the easiest one. You are comfortable owning an outcome without being told how to get there, and you can juggle competing priorities across multiple projects and release cycles.

• Define best-in-class development flows, features, and methodologies for AMD FPGA and Adaptive SoC hardware tools and libraries.
• Influence product definition through the planning team — bringing the customer and field perspective that shapes what gets built, and the technical judgment to say what will and won't work.
• Provide technical expertise to the field and to customers through methodology guidance, training materials, tutorials, reference flows, and user documentation.
• Validate new features and flows against real-world customer designs and complexity before they reach the field.
• Collaborate with engineering, sales, and customers to drive hardware tool features and ensure the smooth launch of new devices and releases.
• Communicate the most complex subjects to the field and to customers, making options, tradeoffs, and impacts clear.
• Evaluate field and customer feedback, identify key areas for new features or changes, and work with planning and engineering to resolve them.
• Serve as a senior technical resource on strategic opportunities and lead high-visibility customer escalations through to resolution.
• Represent AMD at customer design reviews, technical conferences, and industry forums.
• Apply AI agents and copilots to EDA flows and to your own engineering workflow, and help the team raise its bar on how AI is used.

• Excellent working knowledge of RTL and IP-based design flows and expectations.
• Excellent working knowledge of the entire FPGA or ASIC design process and tool flow — synthesis, implementation, timing closure, simulation and verification, and debug.
• Expert in design analysis, experimentation, and methodology.
• Knowledge of Vivado or equivalent depth in a competing FPGA or EDA toolchain.
• Familiarity with SoC architectures and boot flows.
• Ability to handle and solve complex system-level issues, internally and with top-tier customers.
• Track record of influencing what a technical product becomes — through customer advocacy, methodology leadership, or feature definition — in EDA, semiconductor tools, or a related domain.
• Hands-on experience applying AI agents and copilots to drive EDA tools, automate engineering workflows, or solve complex technical problems.
• Excellent written and verbal communication skills, presentation skills, and the ability to work with worldwide teams.

ACADEMIC CREDENTIALS:

• Bachelor's, Master's, or PhD degree in Computer Science, Computer Engineering, Electrical Engineering, with related experience in UVM.

LOCATION:

San Jose, California (preferred) or Longmont, Colorado. Candidates from other locations who are open to relocating to California will be considered.

This role is not eligible for visa sponsorship. 

#LI-BW2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD's “Responsible AI Policy” is available here.

This posting is for an existing vacancy.