Silicon Design Engineer 2 Job Listing at AMD in Shanghai (Job ID 68625-en-us)

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

AMD NBIO DACC (Data Accelerator) team delivers industry leading high-performance DMA engine for AMD Data Center CPU and GPU. DACC is HW implementation of a new DMA engine technology co-developed with AMD's ecosystem partners incorporating virtualization and shared virtual memory capabilities, as well as incorporating additional accelerations functions (CRC, Crypto etc).  DACC is a critical ingredient of AMD's I/O accelerator technology to service today's Mega Data Center ever increasing computing demand. You will work with world class global team on DACC development and verification, provide technical support to various global SOC teams.

THE PERSON:

DACC IP & Subsystem verification, responsible for setting out test plan, building testbench, creating test sequences, meeting regression target, analyzing coverage, and SoC DV support.

KEY RESPONSIBILITIES:

• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for DACC
• Be involved technically in the porting/creation of the DV environment for the new design, block and subsystem level test plan creation and implementation, coverage analysis, and regression cleanup
• Build new testbench or verification components for new features development
• DACC IP/Subsystem level test plan creation and SOC test plan consulting.
• DACC DV/Deployment flow implementation.

PREFERRED EXPERIENCE:

• Complex IP/ASIC/SOC design verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCIe,USB, DDR, DisplayPort)
• Solid background with ASIC design verification flow and multiple ASIC tape out experience
• Solid knowledge on System Verilog, C/C++, Verilog
• Solid knowledge on scripting language like Perl, python, ruby
• Solid knowledge on UVM/OVM
• Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
• Knowledge on High-speed IO/PCIE is a big plus
• Knowledge on IO Virtualization is big plus
• Knowledge on RISC-V is big plus
• Fluent verbal English for technical discussion with global team

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

#LI-JG2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.