Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
The focus of this role is to plan, build, and execute the design of new and existing features for AMD's FCH IP (involving management of system power states, reset, clocking as well as some sub-IP controllers), resulting in no bugs in the final design.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM architecture, AMBA(AXI/AHB/APB) bus, USB(4.0/3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/eSPI/GPIO), General connectivity IPs (I2C/I3C/UART), Ethernet, JTAG, etc.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Understand the ASIC design/verification flow to accomplish targets
- The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, microarchitecture definition, top level SOC design tasks, HDL coding, simulation debugging, timing, silicon debugging, etc.
PREFERRED EXPERIENCE:
- 4+ years experiences with Master degree in Electrical Engineering, Computer Science or related with
- Good understanding on ASIC design verification flow
- Strong RTL coding skills with Verilog/System Verilog and familiar with front-end design flow
- Knowledge in low power design, clock design, etc.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred
- Exposure to leadership or mentorship is an asset.
ACADEMIC CREDENTIALS:
- Master degree in Electrical Engineering, Computer Science or related
Location:
- Beijing or Shanghai
#LI-JG2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
Apply on company website
Find Connections via Linkedin
