Description
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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SMTS SILICON DESIGN ENGINEER
THE ROLE:
Circuit Technology team is looking for a passionate and experienced test chip RTL execution Lead for our high speed PHYs as well as other IPs. This opportunity includes ownership of defining the overall test chip architecture, RTL coding, supporting scan stitching, timing constraints development, supporting ATPG as well as post-silicon bringup.
THE PERSON:
Have strong analytical/problem-solving skills and pronounced attention to details. Must be able to execute hands-on, a self-starter, leader, and able to independently drive tasks to completion.
KEY RESPONSIBILITIES:
Lead and define overall test chip architecture, including the functional and DFX aspects.
Integrate high speed DDR PHY IPs into test chip top level RTL which requires working knowledge of DDR/LPDDR/HBM etc. protocols.
Develop additional custom logic at test chip top level for interfacing and interacting with PHY IP's and associated logic.
Implementation of SOC DFT features (TAP controller, JTAG/IJTAG, GPIOs, ESD structures etc) into RTL.
Gate level simulation using Synopsys VCS and Verdi.
SOC-level SDC development and hand-off to PD
UPF development and hand-off to PD.
ATPG patterns translation from IP level to SOC level and hand-off.
Spyglass bringup and analysis for scan readiness/test coverage gaps.
Run all SOC RTL QA checks (Lint/CDC/RDC/VCLP etc.)
Support silicon bring-up and debug.
Develop efficient DFx flows and methodology compatible with front end and physical design flows
EXPERIENCE & QUALIFICATIONS:
BS/MS/PhD in EE/ECE/CE/CS with at least 10+ years of industry experience in SOC RTL/DFX execution with added exposure to high speed PHY or Serdes IPs design.
Experience with the development of a complete TestChip RTL (including integration of IEEE1149.1 TAP, GPIOs etc) from early RTL design to post-silicon support.
Exposure to MCM (multi-die integration into a package) would be desirable.
Integration of several IPs (with or without integrated JTAG controllers) into the testchip environment.
Experience with integration of PLLs and DFX care-abouts thereby.
Test chip SOC level ICL/PDL transition and implementation.
Understanding of STA fundamentals, experience with SDC development.
Experience with UPF development.
Experience with ATPG patterns translation from IP level to SOC level.
Familiarity with SystemVerilog and UVM.
Strong problem solving and debug skills across various levels of design hierarchies
#LI-PM2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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